Generally, Local Oxidation of Silicon (LOCOS) using a nitride layer has been employed as an isolation technique in the manufacture of semiconductor devices. However, because there are some shortcomings associated with the LOCOS process, new isolation technologies and techniques have been developed. Among the new isolation technologies and techniques are Poly Buffer LOCOS, Recessed LOCOS (R-LOCOS), which have been widely used. These isolation technologies, however, have drawbacks because they are complicated and result in an undesired phenomenon referred to as bird's beak in which inroads are made into an active region by a silicon oxide layer. The drawbacks of these technologies limit the density at which semiconductor devices can be integrated, resulting in a limit of high-integration of the semiconductor device. Furthermore, because a step or surface height differential between the surface of an active region in a silicon substrate and the surface of an oxide layer of a field region is generated, the known isolation techniques typically require a planarization process to be successively performed to reduce the step between the surfaces of the regions.
Recently, an improved Shallow Trench Isolation (STI) process has been introduced. The STI process is advantageous in that it results in excellent isolation properties and occupies a small area so that the STI process may be used in high-integration of semiconductor devices, as compared to a conventional isolation technology.
STI process is performed by forming a trench on a field region of a semiconductor substrate; the trench is then filled with an oxide layer using a Gap Filling process. A Chemical Mechanical Polishing (CMP) is then used to planarize the oxide layer in the trench and the semiconductor substrate, resulting in a field oxide layer that is formed on the field region of the semiconductor substrate. The oxide layer is generally formed using an O3-Tetra-Ethyl-Ortho-Silicate (TEOS) Atmospheric Pressure Chemical Vapor Deposition (APCVD) oxide layer, and a High Density Plasma Chemical Vapor Deposition (HDP CVD) oxide layer. The resulting layer has excellent gap filling and planarization properties.
A conventional STI process will now be described in conjunction with FIG. 1. As shown in FIG. 1, for instance, a multi-insulating layer comprising an oxide layer 11, a nitride layer 13, and an oxide layer 15 are deposited on a front face of a semiconductor substrate 10, which may be a single crystal silicon substrate. Herein, the thickness of the oxide layer 11 is 25 to 200 Å and that of the nitride layer 13 is 1000 to 2000 Å. Then, using a photolithography, a common opening 16 of the oxide layer 11, nitride layer 13, and oxide layer 15 is formed on the field region of the semiconductor substrate 10. Then, using the oxide layer 11, nitride layer 13, and oxide layer 15 as an etching mark layer, the field region of the semiconductor substrate 10 is etched in a desired depth of 3000 to 4000 Å, forming a trench 17 on the field region of the semiconductor substrate 10.
As shown in FIG. 2, an insulating layer such as, for example, an oxide layer 19 is grown in a thickness of 300 to 400 Å on the etched surface in the trench of the semiconductor substrate 10 by a thermal oxidation process. This is performed so as to recover the damaged silicon lattices in the trench 17 in the semiconductor substrate 10 and to restrict leakage current in the oxide layer 21 of FIG. 3 when the oxide layer 21 is buried in the trench 17.
As shown in FIG. 3, using O3-TEOS CVD process, the oxide layer 21 is deposited in a thickness required for burying the trench 17, for example, 5000 to 6000 Å. Of course, instead of the O3-TEOS CVD process, HDP CVD or Low Pressure CVD process can be used.
As is not shown in the drawings, using a conventional CMP process, the oxide layer 21 is planarized and the oxide layer 15, nitride layer 13 and oxide layer 11 all are etched to expose the surface of the active region of the semiconductor substrate 10, thus completing STI process.
In the prior art, the O3-TEOS CVD process is performed by introducing TEOS in a reactor having a temperature of 500 to 600° C. and an atmosphere of O3 so that TEOS is decomposed using an O3 catalyst and a selective deposition of the decomposed object is performed to the surface, thus burying the oxide layer 21 in the trench 17.
However, since the conventional O3-TEOS CVD process is performed in a high temperature of 500 to 600° C. and a high pressure of more than 200 torr, a surface reaction and a vapor phase reaction are simultaneously occurred in the O3 atmosphere. Accordingly, the conventional O3-TEOS CVD process has a poor gap-filling capacity. Thus, the narrower a width of the trench is, the more difficult it is to bury the oxide layer in the trench without generating voids in the trench.
Meanwhile, HDP CVD process, in which an oxide layer is buried in a trench by etching the oxide layer using a plasma deposition or a sputtering, has a burying property superior to that of O3-TEOS CVD process through a combination of a control of velocities of deposition and etching and the whole conditions. However, the HDP CVD process has drawbacks that burying property thereof is dependent upon a shape of trench as the width of trench is narrower and a possibility of damage by plasma is increased.
As described above, the conventional method faces a limit in filling a trench as the trench is narrower.